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Multigig introduces = QuietClock=E2=84=A2 (MQC)=20 family of clock synthesizer ICs for high speed = communications,=20 telecom, networking, server & storage markets. These = clock ICs=20 based on RotaryWave=E2=84=A2 technology break 100 = femtosecond barrier jitter=20 at low power & low phase noise!
QuietClock synthesizers are = programmable clock signal sources that provide an ultra-low = jitter=20 and phase noise reference clock signal to communication, = computing,=20 and networking interface devices. The product family = provides 3.3 V=20 and 2.5 V operation, 1 to 10 outputs from a mix of single = ended=20 (LVCMOS) and differential (LVPECL and LVDS) outputs, and = supports=20 the full industrial temperature range (-40 to 85 degrees=20 Celsius).
The Multigig QuietClock = portfolio=20 includes second source, pin-for-pin replacements of industry = standard products. These encompass the 840001/2/4/51, = 9229/30,=20 12429/30, 843001/11/21/22, and 844001/21 products but with = improved=20 performance, lower power consumption, and lower cost. The = MQC1A0110=20 1:10 buffer provides functional compatibility with the = industry=20 standard 3807 buffer but with twice the frequency (1-400 = MHz) range.=20 Common applications for QuietClock products include Gigabit = Ethernet=20 (GBE), serial Rapid I/O, SONET/SDH, Fibre Channel, = Infiniband, and=20 SATA.
Selected QuietClock = Family=20 Devices:
| Device | Application | Freq (MHz) | # Outs | Package |
|---|---|---|---|---|
| Memory Buffer = Synthesizers | ||||
| SDR/QDR MEM Buffer | 25-400 | 1 LVPECL | 32 pin TQFP | |
| SDR/QDR MEM Buffer | 50-800 | 1 LVPECL | 32 pin TQFP | |
| Ultra-Low Jitter = Synthesizers | ||||
| FC | 106.2, 212.5 | 1 LVCMOS | 8 pin TSSOP | |
| FC | 106.2, 212.5 | 1 LVCMOS | 8 pin TSSOP | |
| GBE, sRIO, Infiniband | 62.5,125,156.25 | 2 LVCMOS | 16 pin TSSOP | |
| 10GBE,XAUI,sRIO | 62.5,125 | 4 LVCMOS | 20 pin TSSOP | |
| 10GBE/GBE | 125 | 1 LVCMOS | 8 pin TSSOP | |
| FC,SONET | 77-81,152-162 | 1 LVCMOS | 8 pin TSSOP | |
| SAS,FC | 50,100,106.25 | 2 LVCMOS/PECL | 16 pin TSSOP | |
| FC | 106.25, 212.5 | 1 LVPECL | 8 pin TSSOP | |
| SONET,SDH | 155.52, 77.76 | 1 LVPECL | 8 pin TSSOP | |
| 10 GBE, GBE, sRIO | 78.125, 156.25 | 1 LVPECL | 8 pin TSSOP | |
| 12 GBE | 93.75, 187.5 | 1 LVPECL | 8 pin TSSOP | |
| 12 GBE | 93.75, 187.5 | 1 LVPECL | 8 pin TSSOP | |
| FC | 100,106.25 | 1 LVPECL | 8 pin TSSOP | |
| 10GBE,GBE | 125 | 1 LVPECL | 8 pin TSSOP | |
| 10GBE,GBE | 62.5,125 | 1 LVPECL | 8 pin TSSOP | |
| 10GBE | 312.5 | 1 LVPECL | 8 pin TSSOP | |
| FC, PCIe | 100, 106.25, 212.5 | 1 LVDS | 8 pin TSSOP | |
| 10 GBE, GBE | 62.5, 125 | 1 LVDS | 8 pin TSSOP | |
| SONET,SDH | 77.76, 155.52 | 1 LVDS | 8 pin TSSOP | |
| 10GBE,GBE,sRIO | 78.125, 156.25 | 1 LVDS | 8 pin TSSOP | |
| 12 GBE | 93.75, 187.5 | 1 LVDS | 8 pin TSSOP | |
| 12 GBE | 93.75, 187.5 | 1 LVDS | 8 pin TSSOP | |
| FC | 100,106.25 | 1 LVDS | 8 pin TSSOP | |
| 10GBE,GBE,sRIO | 156.25 | 1 LVDS | 8 pin TSSOP | |
| Non-Zero Delay Buffers | ||||
| All | 1 =E2=80=93 250 | 10 LVCMOS | 20 pin SOIC,SSOP | |
| All | 1 =E2=80=93 400 | 10 LVCMOS | 20 pin SOIC,SSOP | |
| All | 1 =E2=80=93 250 | 4 LVCMOS | 16 pin SOIC, SSOP | |
| All | 1 =E2=80=93 250 | 6 LVCMOS | 16 pin SOIC, SSOP | |
| All | 1 =E2=80=93 250 | 8 LVCMOS | 20 pin SOIC, SSOP |
=E2=80=A2 Current timing = solutions fail to=20 meet the communications specs
o =
OC-192 (10G/sec=20
SONET) requires less than 1 picosecond jitter at the =
output
o=20
Most systems are not compliant resulting in=20
non-interoperability
o Problem will only gets worse =
beyond=20
OC192
=E2=80=A2 With = QuietClock, specs can be=20 met due to a dramatic reduction in jitter, enabling=20 interoperability
=E2=80=A2 Multigig = products enable 30%-50%=20 power savings while reducing jitter by 3X to 5X.
o Most =
companies=20
have been trying to get lower jitter by throwing =
more
power at=20
it, but unlike an LC Tank, Multigig=E2=80=99s RotaryWave=20
technology
delivers both low jitter & low power.
=E2=80=A2
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